TTL 'Peter Mowry EECC250_Lab6' OPT CRE,MEX *What is stuff on bottom of pg 4 of 8_3? * * This is the CE lab6 Assembly Program * * The serial input from the keyboard is continuously polled until * a new byte is received. This byte is read from the ACIA output port. * Finally the byte's bit pattern is reversed and outputed to PIA port A. * * Author: Peter Mowry * created 9/27/2002 - Began the program largely based on RIT CE notes * (Rochester Institute of Technology Computer Engineering) * modified 9/29/2002 - Wrote Reverse subroutine * modified 10/2/2002 - Wrote Dequeue * modified 10/5/2002 - Wrote Big Loop * modified 10/6/2002 - Fixed problems in Dequeue and Big Loop * ********************** *** EQU statements *** ********************** CMDINT EQU $48C MAX 68000 monitor entry point for future use STACK EQU $23C00 Initial stack pointer START EQU $20000 ROM starting address RAM EQU $22000 pseudo RAM starting address ACIA EQU $E0000 ACIA1 base address PIA EQU $E8001 PIA1 base address] PACR EQU PIA+2 Port A Control Register for PIA1 * when PACR bit #2 = 0, then PADD is selected: PADDR EQU PIA Port A Data Direction Register * when PACR bit #2 = 1, then Data Register is selected: PADR EQU PIA Port A Data I/O Register * PBCR EQU PIA+6 Port B Control Register for PIA1 * when PBCR bit #2 = 0, then PBDD is selected: PBDDR EQU PIA+4 Port B Data Direction Register * when PACR bit #2 = 1, then Data Register is selected: PBDR EQU PIA+4 Port B Data I/O Register * * * ACIA REGISTERS. * ACIACR EQU ACIA ACIA 1 control/status registers ACIADR EQU ACIA+2 ACIA 1 Tx and Rx data registers Priorty0 EQU $f0ff AND with SR to get Priority 0 Priorty7 EQU $0700 OR with SR to get Priority 7 * CSet EQU 1 mask to OR with SR to set Clear bit CClr EQU $FE mask to ANS with SR to clear C-bit * true EQU 1 mask to be moved into messcom for true false EQU 0 mask to be put into messcom for false * RxRDYA EQU 0 bit in ACIA status reg indicating RxDRF int TxRDYA EQU 1 bit in ACIA status reg indicating TxDRE int * * Special characters * CR EQU $0D carriage return LF EQU $0A line feed bell EQU $07 screen bell (beep) * Length constants * byte EQU 1 number of bytes in a byte word EQU 2 number of bytes in a word longword EQU 4 number of bytes in a longword * * Queue structure offsets * Inptr EQU 0 Next insertion pointer (longword) Outptr EQU 4 Next removel pointer (longword) Bufstart EQU 8 first address of circular buffer (L) Bufspill EQU 12 first address beyond circular buf (L) Nunits EQU 16 number of data units enqueued (word) Maxsize EQU 18 maximum number of data units enq'd (W) UnitCode EQU 20 code for size of each data unit (W) * enqueued: 1-bytes, 2-words, 4-long * * Serial output queue structure constants * SerInsize EQU 13 size of serial input queue in bytes SerInunit EQU byte * SerOutsize EQU 18 size of serial output queue in bytes SerOutunit EQU byte serial output units are bytes * Parallel input queue structure constants * ParInsize EQU 13 size of parallel input queue in bytes ParInunit EQU byte parallel inut units are bytes * * Parallel output queue structure constants * ParOutsize EQU 14 size of parallel output queue in bytes ParOutunit EQU byte parallel output units are bytes * C2LowHi equ %00110111 set C2 low, look for C1 rising, enable IRQ C2HiLow equ %00111101 set C2 high, look for C1 falling, enable IRQ C2HiHi equ %00111111 set C2 high, look for C1 rising, enable IRQ C2LowLow equ %00110101 set C2 low, look for C1 falling, enable IRQ C2HiDisable equ %00111110 set C2 high, don't look for C1 rising, disable IRQ * TxIRQEnable equ %10110101 8 data&1 stop, div 16, enable RxIRQ & TxIRQ TxIRQDisable equ %10010101 same as above only disable the TxIRQ * Delay_const equ $00FF00 busy wait delay constant ***************************** *** Execution Code Begins *** ***************************** ORG START Set the origin of the program main MOVE.W #$2700,SR disable processor interrupts MOVEA.L #STACK,SP initialize stack pointer * set Boolean flags MOVE.B #true,Ready4Inp MOVE.B #true,Ready4Out MOVE.B #false,Look4Hi MOVE.B #true,ComplRdy * Form 4 Queue Structures at one time: move.b #50,D2 copy 50 equivalent words lea Qtemplates,A0 from ROM templates into RAM lea SerIn,A1 RAMloop move.w (A0)+,(A1)+ subq.b #1,D2 bne RAMloop * Set up PIA move.b #0,PACR select PADDR move.b #$ff,PADDR make PIA Port A all output bits move.b #0,PBCR select PBDDR move.b #$00,PBDDR make PIA Port B all input bits move.b #C2HiDisable,PACR Set CA2 = 1 and CA1 rising, disable IRQ move.b #C2HiHi,PBCR Set CB2 = 1 and CB1 high-to-low * move.b #C2HiLow,PBCR Set CB2 = 1 and CB1 high-to-low lea SerOut,A0 move.b #CR,D0 send out an initial & in SerOut jsr ENQUEUE move.b #LF,D0 jsr ENQUEUE * Set up ACIA delay * Set up ACIA after short delay to handle "go " command * move.l #Delay_const,D0 DelayLp subq.l #1,D0 bne DelayLp * Initialize ACIA move.b #3,ACIACR Master Reset move.b #TxIRQEnable,ACIACR enable RxIRQ but Enable TxDRE IRQ * Wait for Interrupts in the main program: ANDI.W #Priorty0,SR set running priority to zero * bkgrnd nop nop nop bra bkgrnd ************************************************** * SUBROUTINES ************************************************** ************************************************** * ACIA interrupt routine: ************************************************** ACIA_IRQ ori.w #Priorty7,SR set priority to maximum movem.l D0-D2/A0-A2,-(A7) save registers to be used * For ACIA, we check two bits: * (1) When bit 0 of ACIA SR is 1, means Receiver Interrupt happens; ( if you enable Receiver Interrupt) * (2) When bit 1 of ACIA SR is 1, means Transmit Interrupt happens; * ( if you enable Transmit Interrupt) * Check if Serial Out MOVE.B ACIACR,D2 BTST.B #1,D2 Check ACIACR bit 1 BEQ AC_In if bit 1 is 0, then skip Ser_In JSR Ser_Out * Run Ser_In if bit 0 is 1 AC_In MOVE.B ACIACR,D2 BTST.B #0,D2 Check ACIACR bit 0 BEQ AC_Done If bit 0 is 0, then skip Ser_Out JSR Ser_In *Remember? ACIA interrupts could come from: * (1) There is a Keyboard Input * (2) There is data in the Transmit Data Register *How to know there is ACIA interrupt coming? * btst.b #TxRDYA,D2 * btst.b #RxRDYA,D2 *---- Check previous Lecture “Lab #6 AC_Done movem.l (A7)+,D0-D2/A0-A2 POP registers from stack RTE ************************************************** * Serial Input subroutine; used in ACIA_IRQ ************************************************** Ser_In * Move the new serial input byte from ACIADR to Di MOVE.B ACIADR,D0 * (Re)enable TxDRE interrupts on ACIA for future echoing to screen MOVE.B #TxIRQEnable,ACIACR * Is new input byte ? CMPI #CR,D0 BEQ Is_CR If it is a Carriage Return Not_CR * enqueue new input byte into SerOut for echoing to screen LEA SerOut,A0 JSR ENQUEUE * Meanwhile enqueue the new input byte into SerIn LEA SerIn,A0 JSR ENQUEUE * If enqueue was NOT successful then enqueue a “BELL” into SerOut BCC SI_Done MOVE.B #bell,D0 LEA SerOut,A0 JSR ENQUEUE BRA SI_Done Is_CR * Enqueue both a and into SerOut MOVE.B #CR,D0 LEA SerOut,A0 JSR ENQUEUE MOVE.B #LF,D0 LEA SerOut,A0 JSR ENQUEUE * Dequeue each byte from SerIn and enqueue into ParOut *SIPO_Rep LEA SerIn,A0 * JSR DEQUEUE * BCS SIPO_Fin If Fail, then no bytes left * LEA ParOut,A0 * JSR ENQUEUE * BRA SIPO_Rep Repeat until SerIn is empty * All of SerIn to ParOut SIPO_Rep LEA SerIn,A0 JSR DEQUEUE BCS SIPO_Fin If Fail, then no bytes left LEA ParOut,A0 JSR ENQUEUE BRA SIPO_Rep Repeat until SerIn is empty * When SerIn has been completely emptied, enqueue a final into ParOut SIPO_Fin LEA ParOut,A0 MOVE.B #CR,D0 JSR ENQUEUE * IF Ready4Out =TRUE and ComplRdy = TRUE THEN * CMPI.B #1,Ready4Out * BNE SI_Done * If ComplRdy = TRUE CMPI.B #1,ComplRdy BNE SI_Done * Dequeue a byte from ParOut (there should be at least one, the ) LEA ParOut,A0 JSR DEQUEUE * Invoke the subroutine that implements the Parallel Output activity JSR SendParOut SI_Done RTS ************************************************** * Serial Output subroutine; used in ACIA_IRQ ************************************************** Ser_out *If the ACIA is ready to send another output byte: * MOVE.B ACIACR,D2 copy ACIA1 status register into D2 * BTST.B #1,D2 see if RxReady bit is set * BEQ SO_Done Skip if ACIA is not ready * Attempt to dequeue a character from SerOut LEA SerOut,A0 JSR DEQUEUE BCS SO_Failed Dequeue failed * If dequeue was successful * Send that character to ACIA (MOVE.B D0,ACIADR) MOVE.B D0,ACIADR * Be sure to (re)enable TxDRE interrupts (Set ACIACR = TxIRQEnable = %10110101) MOVE.B #TxIRQEnable,ACIACR BRA SO_Done * If dequeue was unsuccessful (means SerOut is empty) * Disable TxDRE interrupts on ACIA (Set ACIACR =TxIRQDisable = %10010101) SO_Failed MOVE.B #TxIRQDisable,ACIACR SO_Done RTS ************************************************** * PIA Interupt Routine ************************************************** PIA_IRQ ori.w #Priorty7,SR set priority to maximum MOVEM.L D0-D2/A0-A2,-(A7) save registers to be used * PIA CB1 active edges have their interrupts always enabled * If Ready4Inp = TRUE CMPI.B #true,Ready4Inp BNE PIAskip1 * Check CB1 Flag: * IF CB1 Flag = 1 (in bit 7 of PBCR) BTST.B #7,PBCR BEQ PIAskip1 Equal means bit 7 is zero * THEN * Get input byte from PIA Port B MOVE.B PBDR,D0 * Check if it was a . CMPI.B #CR,D0 BEQ PI_CR * If input byte was NOT a * THEN * Blindly enqueue it into ParIn (don’t worry if queue is full, trash it) LEA ParIn,A0 JSR ENQUEUE * Set CB2 = 0 and look for rising edge on CB1 (Set PBCR to C2LowHi) MOVE.B #C2HiHi,PBCR * Set Ready4Inp = FALSE MOVE.B #false,Ready4Inp * Exit Parallel Input Routine BRA ExitPIR * If input byte was a * THEN * Enqueue a leading and into SerOut PI_CR LEA SerOut,A0 MOVE.B #CR,D0 JSR ENQUEUE LEA SerOut,A0 MOVE.B #LF,D0 JSR ENQUEUE * Dequeue each byte from ParIn and enqueue into SerOut PISO_Rep LEA ParIn,A0 JSR DEQUEUE BCS PISO_Fin If Fail, then no bytes left LEA SerOut,A0 JSR ENQUEUE BRA PISO_Rep Repeat until ParIn is empty * When queue ParIn has been emptied, * then enqueue a trailing and into SerOut PISO_Fin LEA SerOut,A0 MOVE.B #CR,D0 JSR ENQUEUE LEA SerOut,A0 MOVE.B #LF,D0 JSR ENQUEUE * Whenever anything is enqueued into SerOut, (re)enable ACIA * TxDRE interrupts. MOVE.B #TxIRQEnable,ACIACR * Exit Parallel Input Routine BRA ExitPIR * END of all previous IFs PIAskip1 * IF Ready4Inp = FALSE: * Check CB1 Flag: * IF CB1 Flag = 1 (in bit 7 of PBCR) BTST #7,PBCR BEQ ExitPIR Skip if bit 7 is zero * THEN * Set Ready4Inp = TRUE MOVE.B #true,Ready4Inp * Dummy read of PBDR to clear interrupt generated on rising edge of CB1 MOVE.B PBDR,D2 * Set CB2 = 1 and look for falling edge on CB1 (set PBCR = C2HiLow) MOVE.B #C2HiLow,PBCR * Check CA1 Flag: * IF CA1 Flag = 1 (bit 7 of PACR) ExitPIR BTST #7,PACR BEQ EndPIO Done with PIO if CA1=0 * If bit 7 of PACR is 1 * Do a dummy read of PADR to clear interrupt request MOVE.B PADR,D2 * If Look4Hi = false CMPI.B #0,Look4Hi BNE PI_Else Else if not false MOVE.B #C2LowHi,PACR MOVE.B #false,Ready4Out MOVE.B #true,Look4Hi BRA EndPIO PI_Else MOVE.B #true,Ready4Out MOVE.B #C2HiHi,PACR * Attempt to dequeue byte from ParOut LEA ParOut,A0 JSR DEQUEUE BCS PI_Failed * Dequeue succeess JSR SendParOut BRA EndPIO * Dequeue failed PI_Failed MOVE.B #true,ComplRdy MOVE.B #true,Ready4Out MOVE.B #C2HiDisable,PACR EndPIO MOVEM.L (A7)+,D0-D2/A0-A2 POP registers from stack RTE ************************************************** * Use SendParOut when you've really decided to send a parallel output byte * D0 contains byte to be sent ************************************************** SendParOut MOVE.B D0,PADR send byte MOVE.B #C2LowLow,PACR MOVE.B #false,Ready4Out MOVE.B #false,Look4Hi MOVE.B #false,ComplRdy RTS *Parallel Interrupt Subroutine *ParInSr *In this subroutine, you may need to DeQ Par_in and then EnQ Ser_out, *Notice that sometimes we need to check CCR-C, sometimes we don’t. *Just make sure everything is safe. *You don’t want to DeQ an empty Queue, do you? * RTS *I don't really use this mb either *PISRloop * JSR DEQUEUE dequeue character from parallel input queue * BCS PISR done * JSR EnQ enqueue character into serial output queue * BRA PISRloop if not, repeat loop * RTS ******** Enq Subroutine ********************************************** * ENQUEUE subroutine - it expects the data element to be * enqueued to be right justified in register D0. It also * expects register A0 to point to the queue's structure. If * there's room in the queue, the enqueuing operation will be * successful and the Carry-bit (the C-bit) will be cleared. * If there was no room for the data element, the Carry-bit * will be set upon return to the calling routine. * This subroutine destroys the contents of registers D1 & A1. * revised 3/28/91 ********************************************************************** ENQUEUE MOVE.W Nunits(A0),D1 first see if there's CMP.W MaxSize(A0),D1 room for data element BLO ENQOK If so, go to ENQOK * * If we "fall through" to here, there's no room. Set * Carry-bit C, then return * ORI.B #%00001,CCR Set Carry-bit to "1" RTS Return to calling routine ENQOK ADDQ.W #1,Nunits(A0) increment number of data * elements enqueued MOVEA.L Inptr(A0),A1 get insertion pointer to A1 * * Now test if longword, word, or byte size data element to * be enqueued by checking UnitCode in queue structure: * CMPI.W #word,UnitCode(A0) BHI ENQLONG if UnitCode > #word, must be L.W. BEQ ENQWORD if it's =, must be word * * If we fall through, assume it's a byte * MOVE.B D0,(A1)+ enqueue byte data element BRA ENQChkSpill * ENQLONG MOVE.L D0,(A1)+ enqueue longword data element BRA ENQChkSpill * ENQWORD MOVE.W D0,(A1)+ enqueue word data element * * Now see if we incremented insertion pointer in A1 past buffer: * ENQChkSpill CMPA.L Bufspill(A0),A1 If they're =, we must BLO ENQStPtr fix Inptr to Bufstart * * Fix Inptr to top of circular buffer found in Bufstart * MOVEA.L Bufstart(A0),A1 * ENQStPtr MOVE.L A1,Inptr(A0) store modified Inptr ANDI.B #%11110,CCR clear Carry-bit RTS normal return from subroutine * ******Dequeue Subroutine********************************************** * * To DEQUEUE, one must set Address Register A0 to point * to the queue's descriptor structure, call the DEQUEUE * subroutine; the dequeued data item (byte, word or longword) * will be right-justified in data register D0. Upon return * if the Carry-bit is clear the dequeue was successful, if * the Carry-bit is set, the dequeue was unsuccessful - i.e. * an attempt was made to dequeue an item from an empty * queue. * * LEA Q1struct,A0 point at Q1's structure * JSR DEQUEUE * * BCC SUCCESS if a data element was successfully * dequeued right justified into D0 * or * BCS FAILURE if attempting to dequeue an * element from an empty queue * * * DEQUEUE subroutine will dequeue a data element * right justified in register D0. It also * expects register A0 to point to the queue's structure. If * there's data in the queue, the dequeuing operation will be * successful and the Carry-bit (the C-bit) will be cleared. * If the queue was empty, the Carry-bit * will be set upon return to the calling routine. * This subroutine destroys the contents of registers D1 & A1. ********************************************************************** DEQUEUE * MOVE.W Nunits(A0),D1 first see if there are any * CMP #0,D1 elements to dequeue * BLO DEQOK If so, go to DEQOK TST.W Nunits(A0) BNE DEQOK * * If we "fall through" to here, there's no room. Set * Carry-bit C, then return * ORI.B #%00001,CCR Set Carry-bit to "1" RTS Return to calling routine DEQOK SUBQ.W #1,Nunits(A0) increment number of data * elements enqueued MOVEA.L Outptr(A0),A1 get insertion pointer to A1 * * Now test if longword, word, or byte size data element to * be enqueued by checking UnitCode in queue structure: * CMPI.W #word,UnitCode(A0) BHI DEQLONG if UnitCode > #word, must be L.W. BEQ DEQWORD if it's =, must be word * * If we fall through, assume it's a byte * MOVE.B (A1)+,D0 copy byte data element BRA DEQChkSpill * DEQLONG MOVE.L (A1)+,D0 copy long data element BRA DEQChkSpill * DEQWORD MOVE.W (A1)+,D0 copy word data element * * Now see if we incremented insertion pointer in A1 past buffer: * DEQChkSpill CMPA.L Bufspill(A0),A1 If they're =, we must BLO DEQEndPtr fix Inptr to Bufstart * * Fix Inptr to top of circular buffer found in Bufstart * MOVEA.L Bufstart(A0),A1 * DEQEndPtr MOVE.L A1,Outptr(A0) store modified Inptr ANDI.B #%11110,CCR clear Carry-bit RTS normal return from subroutine ********************************************************** * * "Constants" Data definitions and storage allocation: * org $21000 * ?? ?? ******************************************************************* * * * Example structure definition as a ROM template which would * be copied into the actual RAM queue structures at runtime. * We can count on assembler to preload initialization values * into ROM, but certainly NOT RAM! * Qtemplates dc.l SerInBuf Inptr dc.l SerInBuf Outptr dc.l SerInBuf Bufstart dc.l SerInBuf+(SerInsize*SerInunit) Bufspill dc.w 0 dc.w SerInsize dc.w SerInunit * dc.l SerOutBuf Inptr dc.l SerOutBuf Outptr dc.l SerOutBuf Bufstart dc.l SerOutBuf+(SerOutsize*SerOutunit) Bufspill dc.w 0 Nunits dc.w SerOutsize Maxsize dc.w SerOutunit UnitCode * dc.l ParInBuf Inptr dc.l ParInBuf Outptr dc.l ParInBuf Bufstart dc.l ParInBuf+(ParInsize*ParInunit) Bufspill dc.w 0 Nunits dc.w ParInsize Maxsize dc.w ParInunit UnitCode * dc.l ParOutbuf Inptr dc.l ParOutbuf Outptr dc.l ParOutbuf Bufstart dc.l ParOutbuf+(ParOutsize*ParOutunit) Bufspill dc.w 0 Nunits dc.w ParOutsize Maxsize dc.w ParOutunit UnitCode * dc.b 0,0,0,0,0,0 some zeroes for initializing flag bytes *----- Use DC directive to define Queue Structure TEMPLATE …* * ?? ?? ********************************************************** * RAM variables area ********************************************************** ORG $22000 SerIn ds.w 11 Serial Input Queue Structure SerOut ds.w 11 Serial Output Queue Structure ParIn ds.w 11 Parallel Input Queue Structure ParOut ds.w 11 Parallel Output Queue Structure * Some Variables: messcom ds.b 1 message complete flag DSerRout ds.b 1 SISerRout ds.b 1 SOSerRout ds.b 1 PISerRout ds.b 1 POSerRout ds.b 1 copyACIACR ds.b 1 copy of ACIA Status Register Ready4Inp ds.b 1 Boolean flags for parallel handshaking Ready4Out ds.b 1 Look4Hi ds.b 1 ComplRdy ds.b 1 * * Define Queue Buffer: SerInbuf ds.b SerInsize*SerInunit SerOutbuf ds.b SerOutsize*SerOutunit ParInbuf ds.b ParInsize*ParInunit ParOutbuf ds.b ParOutsize*ParOutunit * ********************************************************** * Set Autovector Jump Address: * ORG $23E18 Autovector Level 5 for PIAs JMP PIA_IRQ * ORG $23E1E Autovector Level 6 for ACIA JMP ACIA_IRQ * ORG $23E12 Autovector Level 4 for Timer * JMP TIMER_IRQ end main